`include "../../define.svh"
module int_mult_top (
    input clk,
    input [31:0] int_a_in,
    input [31:0] int_b_in,
    input [1:0] data_type,
    output reg signed [31:0] int_out
);
    // 输入预处理（提取有效位）
    //-------------------------------------
    wire signed [7:0] a_int8 ;
    assign a_int8 = int_a_in[7:0];  // 提取低8位
    wire signed [3:0] a_int4 ;
    assign a_int4 = int_a_in[3:0];  // 提取低4位
    wire signed [7:0] b_int8 ;
    assign b_int8 = int_b_in[7:0];
    wire signed [3:0] b_int4 ;
    assign b_int4 = int_b_in[3:0];

    // 统一补全到8位（int4扩展至8位）
    //-------------------------------------
    wire signed [7:0] a_unified;
     assign a_unified= (data_type == `INT4) ? 
        { {4{a_int4[3]}}, a_int4 } :  // int4符号扩展至8位
        a_int8;                      // int8直接使用
    
    wire signed [7:0] b_unified;
     assign b_unified= (data_type == `INT4) ? 
         { {4{b_int4[3]}}, b_int4 } : 
        b_int8;

    // 8位有符号乘法与结果扩展
    //-------------------------------------
    wire signed [15:0] product_16bit;
     assign product_16bit= a_unified * b_unified;  // 8x8=16位乘法
    wire signed [31:0] product_ext;
       assign product_ext= {{16{product_16bit[15]}}, product_16bit}; // 符号扩展至32位

    //-------------------------------------
    // 输出控制
   //assign int_out = int_en ? product_ext : 32'd0;
     always @(posedge clk) begin
            int_out <= product_ext;
        end 
        //assign int_out = product_ext;
endmodule